1. Field of the Invention
This invention relates to a clamping circuit clamping a pedestal level, for example, of a video signal.
2. Related Art Statement
FIG. 5 is a formation diagram showing a related art of a clamping circuit.
FIG. 5 shows an example made an IC. The clamping circuit is formed of an IC block 4 shown on the right side from the broken line in the diagram and a capacitor 2 combining a coupling and clamping capacity. A signal from a signal source 1 is fed to an input terminal 5 of the IC block 4 through the capacitor 2. The signal appearing at the input terminal 5 is fed to a circuit in the next step not illustrated and is given also to a reversing input end of a comparing circuit 3. A reference level signal V ref has been given to a non-reversing input end of the comparing circuit 3. A clamping pulse has been also given to the comparing circuit 3. During this clamping pulse period, the comparing circuit 3 compares the signal level of the input terminal 5 and the level of the reference level signal with each other and outputs a current output based on the difference between them to the input terminal 5 from the output end. That is to say, the signal level of the input terminal 5 during the clamping pulse period will be clamped to the level of the reference level signal.
The clamping operation in the case that the signal from the signal source 1 is, for example, a video signal shall be explained in the following.
The video signal has a flyback period consisting of a synchronizing signal period, front porch period and back porch period, and a scanning period. The scanning period is a signal period in which the amplitude varies alternately. The front porch and back porch periods in the flyback period are flat periods in which the amplitude is flat (pedestal level). The video signal given to the input terminal 5 of the IC block 4 through the capacitor 2 is fed to the reversing input end of the comparing circuit 3. In the period of the clamping pulse input in the flat period, for example, the back porch period, the comparing circuit 3 compares the pedestal level of the video signal and the level of the reference level signal with each other and gives a current output based on the difference between them to the input terminal 5. The charged and discharged power amount of the capacitor 2 in the clamping pulse period will be controlled by the current output from the comparing circuit 3 and, after all, the pedestal level of the input terminal 5 will coincide with the level of the reference level signal. That is to say, a video signal in which the pedestal level is defined by the level of the reference level signal will be obtained at the input terminal 5. Thus, the direct current part of the video signal can be reproduced.
Another formation is possible as of a clamping circuit. However, according to the formation in FIG. 5, a clamping capacity and input coupling capacity can be used as combined, two capacitors are not required and therefore the number of pins can be reduced so as to be adapted to an IC circuit.
FIG. 6 is a formation diagram showing a related art of a clamping circuit preset in a matrix circuit forming a primary color signal from a luminance signal and color difference signals.
In the circuit in FIG. 6, the clamping circuits in FIG. 5 are provided respectively for three R, G and B axes and the signals from signal sources 1a, 1b and 1c are respectively color difference signals B-Y and R-Y and a luminance signal Y. These color difference signals B-Y and R-Y and luminance signal Y are given to input terminals 5a, 5b and 5c respectively through capacitors 2a, 2b and 2c for coupling and clamping.
A reference level signal has been given to comparing circuits 3a, 3b and 3c which output current outputs for making the pedestal levels of the signals appearing respectively at the input terminals 5a, 5b and 5c coincide with the reference level signal. A matrix circuit 6 matrix-processes the color difference signals R-Y and B-Y and luminance signal Y to form three primary color outputs G out, B out and R out. When a reference level signal of the same level is given to the comparing circuits 3a, 3b and 3c, the pedestal levels of the color difference signals R-Y and B-Y and luminance signal Y input into the matrix circuit 6 will all become equal to the level of the reference level signal. The matrix circuit 6 makes a matrix process while maintaining the pedestal level of the input video signal. It is easy to set the operating dynamic range and output level of the matrix circuit 6.
However, a lag will be produced in the pedestal levels of the output three primary color signals G out, B out and R out by a difference in the matrix process in the matrix circuit 6. When the signal thus lagged in the direct current level is given to such non-linear circuit as a .gamma. correcting circuit, the characteristics of this non-linear circuit will remarkably vary.
The pedestal levels of the luminance signal Y and color difference signals B-Y and R-Y can be adjusted by independently setting the reference level signal given to the respective comparing circuit 3a, 3b and 3c but the pedestal levels of the primary color outputs G out, B out and R out from the matrix circuit 6 can not be independently adjusted. Therefore, in order to adjust the direct current level of one output of the primary color outputs G out, B out and R out, the reference level signals given to the respective comparing circuits 3a, 3b and 3c must be all adjusted and all the direct current levels of the B-Y, R-Y and Y signals must be re-adjusted. In case a .gamma. correcting circuit in which the correction characteristic is determined by the pedestal level is adopted in the next step of the matrix circuit 6, when the reference level signal given to the respective comparing circuits 3a, 3b and 3c is adjusted, the .gamma. correcting characteristic will also vary. Therefore, there has been a problem that it is very difficult to adjust the respective primary color outputs.
In order to solve this problem, the output of the matrix circuit 6 may be clamped once more. However, in such case, it will be necessary to provide for each axis a clamping capacitor for clamping the primary color outputs G out, B out and R out and the number of pins will increase to be at least three pins more than in the circuit in FIG. 6. This is not advantageous to the IC in which the number of pins is limited.